This Makes My RISC-V Trap Handler Does Not Work

I was working on a RISCV assembly when suddenly I got a weird issue.

The exception does not get caught in the trap handler. I thought this was a QEMU bug on the RISCV target because the trap handler works on my other code.

Then after a day of digging, I figured out that it was the mtvec needs to be aligned on 4-byte, as mentioned on the privileged ISA.

The value in the BASE field must always be aligned on a 4-byte boundary, and the MODE setting may impose additional alignment constraints on the value in the BASE field

Finally, simply by replacing the value of mtvec with a multiple of 4-bytes, the exception can be trapped by the trap handler and functioning properly.

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